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IEEE Computer Architecture Letters 中科院4区 JCR:Q4 SCIE EI IEEE JST
发文量 824
被引量 12,798
影响因子(2025版) 0.724

IEEE Computer Architecture Letters (CAL) is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors,  workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect achitectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques,  domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.

  • 主办单位: IEEE COMPUTER SOC
  • 出版地区: LOS ALAMITOS
  • 出版周期: 年2期
  • 别名: IEEE COMPUT ARCHIT L;IEEE COMPUT ARCHIT LETT;IEEE Comput. Archit. Lett.;IEEE COMPUTER ARCHITECTURE LETTERS
  • 国际标准连续出版物号/电子版 ISSN 1556-6056 / EISSN 1556-6064
  • 创刊时间: 2002年
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期刊信息

  • 主办单位:IEEE COMPUTER SOC
  • 主  编:Sudhanva Gurumurthi
  • 地  址: LOS ALAMITOS
  • 电子邮件: gsudhanva@gmail.com(Chief Editor,Sudhanva Gurumurthi)

期刊简介

IEEE Computer Architecture Letters (CAL) is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors,  workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect achitectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques,  domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.